PCM1606E SSOP16
timing requirements
system clock input
The PCM1606 requires a system clock for operating the digital interpolation filters and multilevel delta-sigma
modulators. The system clock is applied at the SCKI (pin 20). Table 1 shows examples of system clock
frequencies for common audio sampling rates.
Figure 1 shows the timing requirements for the system clock input. For optimal performance, it is important to
use a clock source with low phase jitter and noise. Texas Instruments’ PLL1700 multiclock generator is an
excellent choice for providing the PCM1606 system clock source.
The 192-kHz sampling frequency operation is available on DATA1 for VOUT1 and VOUT2. When the system clock
of 128 fS or 192 fS is detected, VOUT3, VOUT4, VOUT5 and VOUT6 are automatically forced to the bipolar zero
level (= 0.5 VCC). Table 1 lists the typical system clock frequency.
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توضیحات
24-BIT/ 192-kHz SAMPLING/ 6-CHANNEL/ ENHANCED MULTILEVEL/ DELTA-SIGMA DIGITAL-TO-ANALOG CONVERTER
DESCRIPTION
The PCM1606 is a CMOS monolithic integrated circuit
that features six 24-bit audio digital-to-analog
converters and support circuitry in a small 20-lead
SSOP package. The digital-to-analog converters utilize
Texas Instruments’ enhanced multilevel, delta-sigma
architecture, which employs 2nd-order noise shaping
and 8-level amplitude quantization to achieve excellent
signal-to-noise performance and a high tolerance to
clock jitter.
The PCM1606 accepts industry-standard audio data
formats with 16- to 24-bit audio data. Sampling rates up
to 200 kHz are supported.
توضیحات تکمیلی
| Package |
SSOP16 |
|---|---|
| کیفیت |
original |
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